#ifndef MAC_REG_TX_BRFEC_H
#define MAC_REG_TX_BRFEC_H

/* Base address of Module's Register */
#define CSR_TX_BRFEC_BASE (0x1e000)

#define CSR_TX_BRFEC_INT_STATUS (CSR_TX_BRFEC_BASE + 0x0)
#define CSR_TX_BRFEC_INT_ENABLE (CSR_TX_BRFEC_BASE + 0x4)
#define CSR_TX_BRFEC_INT_SET (CSR_TX_BRFEC_BASE + 0x8)
#define CSR_TX_BRFEC_PHY_RSTN (CSR_TX_BRFEC_BASE + 0x20)
#define CSR_TX_BRFEC_PHY0_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x40)
#define CSR_TX_BRFEC_PHY0_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x44)
#define CSR_TX_BRFEC_PHY0_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x48)
#define CSR_TX_BRFEC_PHY0_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x4c)
#define CSR_TX_BRFEC_PHY0_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x50)
#define CSR_TX_BRFEC_PHY0_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x54)
#define CSR_TX_BRFEC_PHY1_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x60)
#define CSR_TX_BRFEC_PHY1_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x64)
#define CSR_TX_BRFEC_PHY1_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x68)
#define CSR_TX_BRFEC_PHY1_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x6c)
#define CSR_TX_BRFEC_PHY1_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x70)
#define CSR_TX_BRFEC_PHY1_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x74)
#define CSR_TX_BRFEC_PHY2_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x80)
#define CSR_TX_BRFEC_PHY2_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x84)
#define CSR_TX_BRFEC_PHY2_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x88)
#define CSR_TX_BRFEC_PHY2_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x8c)
#define CSR_TX_BRFEC_PHY2_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x90)
#define CSR_TX_BRFEC_PHY2_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x94)
#define CSR_TX_BRFEC_PHY3_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0xa0)
#define CSR_TX_BRFEC_PHY3_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0xa4)
#define CSR_TX_BRFEC_PHY3_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0xa8)
#define CSR_TX_BRFEC_PHY3_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0xac)
#define CSR_TX_BRFEC_PHY3_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0xb0)
#define CSR_TX_BRFEC_PHY3_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0xb4)
#define CSR_TX_BRFEC_PHY4_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0xc0)
#define CSR_TX_BRFEC_PHY4_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0xc4)
#define CSR_TX_BRFEC_PHY4_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0xc8)
#define CSR_TX_BRFEC_PHY4_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0xcc)
#define CSR_TX_BRFEC_PHY4_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0xd0)
#define CSR_TX_BRFEC_PHY4_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0xd4)
#define CSR_TX_BRFEC_PHY5_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0xe0)
#define CSR_TX_BRFEC_PHY5_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0xe4)
#define CSR_TX_BRFEC_PHY5_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0xe8)
#define CSR_TX_BRFEC_PHY5_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0xec)
#define CSR_TX_BRFEC_PHY5_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0xf0)
#define CSR_TX_BRFEC_PHY5_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0xf4)
#define CSR_TX_BRFEC_PHY6_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x100)
#define CSR_TX_BRFEC_PHY6_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x104)
#define CSR_TX_BRFEC_PHY6_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x108)
#define CSR_TX_BRFEC_PHY6_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x10c)
#define CSR_TX_BRFEC_PHY6_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x110)
#define CSR_TX_BRFEC_PHY6_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x114)
#define CSR_TX_BRFEC_PHY7_SYNC_HEAD_ERR_DET (CSR_TX_BRFEC_BASE + 0x120)
#define CSR_TX_BRFEC_PHY7_DBG_ERR_CTRL (CSR_TX_BRFEC_BASE + 0x124)
#define CSR_TX_BRFEC_PHY7_DBG_ERR_INS_EN (CSR_TX_BRFEC_BASE + 0x128)
#define CSR_TX_BRFEC_PHY7_DBG_ERR_INS_DONE (CSR_TX_BRFEC_BASE + 0x12c)
#define CSR_TX_BRFEC_PHY7_DBG_ERR_INS_CNT (CSR_TX_BRFEC_BASE + 0x130)
#define CSR_TX_BRFEC_PHY7_DBG_HIS_ST (CSR_TX_BRFEC_BASE + 0x134)
#define CSR_TX_BRFEC_SPARE (CSR_TX_BRFEC_BASE + 0x140)
#define CSR_TX_BRFEC_SPARE_CNT (CSR_TX_BRFEC_BASE + 0x144)

#endif